CS 501-Advance Computer Architecture |Solved Current Grand Quiz Mid terms#2021

CS 501-Advance Computer Architecture Solved Current Grand Quiz Mid terms#2021 (1)
CS 501-Advance Computer Architecture Solved Current Grand Quiz Mid terms#2021 (1)

CS 501-Advance Computer Architecture |Solved Current Grand Quiz Mid terms#2021

SPEC  stands for_______________

  1. Scientific performance Evaluation Cooperative
  2. Scientific performance Execution Cooperative
  3. System performance Execution Cooperative 
  4. System performance Evaluation Cooperative

Type D instruction format of SRC includes ____________ALU registers.

  1. 3
  2. 1
  3. 4
  4. 2

Which type of exceptions rise during the process of decoding and executing the instance

  1. Non-mask able Exceptions
  2. Interrupts (External Exceptions)
  3. program Exceptions
  4. Hardware Exceptions

In the case of a constant, variable, an address or (label-PC), the unconditional jump.

  1. from -64 to 63
  2. from -128 to 127
  3. from -327 to 32767
  4. from -256 to 255

jump [ra+c2 is an ______________instruction

  1. Unconditional jump
  2. Conditional jump
  3. Shift
  4. Arithmetic and logic

There are __________ types of reset operations in SRC

  1. Four
  2. Three
  3. Two
  4. Five

Which of the following registers is used as an implicit operand in MUL/D

  1. IR
  2. PC
  3. R0
  4. SP

Which of the following is NOT an advantage of using register-to-register data transfered

  1. It is faster
  2. It is simpler
  3. It is most compact
  4. It is easier to pipeline

Which of the following is responsible for generating signals for external events?

  1. Exception generation
  2. “CON” control signal
  3. Interrupt generator
  4. Control unit signals generator

While executing the RTL instruction A—R3 which of the given below control signals will be

  1. LA. R3out
  2. R3in. Lout
  3. LA. R3in
  4. R3out

In SRC ,which of the following is a notation which is used to represent 32-bit memory word are

  1. M[56]<31-0> :=M[59] M[58] M[57] M[56]
  2. M[56]<31-0> :=M[56] M[57] M[58] M[59]
  3. M[56]<0-31> :=M[59] M[57] M[58] M[59]
  4. M[56]<0-31> :=M[59] M[58] M[57] M[56]

In SRC, he general-purpose register file includes _________registers, each 32 bit

  1. 24 registers R0 to R23
  2. 32 registers R0 to R31
  3. 16 registers R0 TO R15
  4. 64 registers R0 to R63

CS 501-Advance Computer Architecture |Solved Current Grand Quiz Mid terms#2021

“Finite-state machine ” concepts are usually to represent the Control Unit where every state

  1. 16
  2. 1
  3. 2
  4. 4

Which of the following types of unconditional jump is also known as near jump?

  1. Register relative
  2. Direct
  3. Indirect
  4. PC relative

For any of the instructions that are a part of the instruction set of the SRC, registers or the appropriate memory location.

  1. Registers
  2. None of the given
  3. Control signals 
  4. Memory

In case of FALCON-A, __________ instruction are present which are not present in the SRC processor.

  1. open and close
  2. in and out
  3. read and write
  4. create and destroy

RISC stand for ?

  1. Registers internal system cache
  2. Register Instruction Set Computer
  3. Reduced Internal System Computers 
  4. Reduced Instruction Set Computer

During the RESET operation of processor, control step counter is set to ___________

  1. 0
  2. 1
  3. -1
  4. 2

In MC68000,____________ register is used as stack pointer.

  1. D7
  2. D0
  3. A7
  4. A0

To implement an N-bit barrel shifter in form of a combinational circuit. we require N ______

  1. selectors
  2. demultiplexers
  3. multiplexers
  4.  tri-state buffers

___________control signal allows the contents of the program computer register to be written onto the internal processor but

  1. PCout
  2. InC4
  3. LC
  4. LPC

What does the word ‘D’ in the ‘D-flip-Flop’ stand for ?

  1. data 
  2. dynamic
  3. double
  4. Digital

A___________ processor is based on a very long instruction word.

  1. SRC
  4. VLIW

In EAGLE processor, Which of the following notations is used to represent a memory word stored at address 8?

  1. M[8]<0–15> ;=M [9]@ M[8]
  2. M[8]<15–0> ;=M [8]@ M[9]
  3. M[8]<0–15> ;=M [8]@ M[9]
  4. M[8]<15–0> ;=M [9]@ M[8]

In Falcon-A processor, first 5 most significant bits from the IR are fed to a _________

  1. 5-to-31
  2. 5-to-32
  3. 11-to-15
  4. 5-to-10

In which of the following addressing modes, the address of the memory from where the value is to be accessed is given in the instruction?

  1. Register Direct Addressing
  2. Indirect Addressing
  3. Direct Addressing
  4. Immediate Addressing

The instruction “PUSH A” is an example of

  1. 1- address instruction
  2. 0- address instruction
  3. 2- address instruction
  4. 3- address instruction

The____________ control signal enables the input to the register C for writing the incremented value of PC onto it.

  1. INC4
  2. PCout
  3. LPC
  4. LC

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